It is conventional in the electronic industry to encapsulate one or more semiconductor devices, such as integrated circuit dies, or chips, in a semiconductor package. These plastic packages protect a chip from environmental hazards, and provide an apparatus for electrically and mechanically attaching the chip to an intended device. Such semiconductor packages have included metal lead frames for supporting an integrated circuit chip which is bonded to a chip paddle region formed centrally therein. Bond wires that electrically connect pads on the integrated circuit chip to individual leads of the lead frame are then incorporated. A hard plastic encapsulating material that covers the bond wire, the integrated circuit chip, and other components forms the exterior of the package.
As the integration density of semiconductor chips increases, the number of pads of each semiconductor chip increases. However, semiconductor packages are being continuously demanded to be smaller and lighter with an increasing demand for portable semiconductor products. Further, reductions in cost and increases in reliability in the manufacturing of the packages are demanded.
According to such miniaturization tendencies, semiconductor packages, which transmit electrical signals from semiconductor chips to motherboards and support the semiconductor chips on the motherboards, have been designed to have a small size. Examples of such semiconductor packages are referred to as MLP (molded leadless package) type semiconductor packages. During the manufacturing for a semiconductor package, electrical testing is required to insure proper function of the semiconductor package. This testing occurs after the semiconductor package has been separated from a matrix of semiconductor packages by singulation.
Conventionally, in a molded leadless package (MLP), the features of a semiconductor chip are connected to the leads of the leadframe by bond wires, for example see U.S. Pat. No. 6,475,827 issued to Lee, et al. Such bond wires are typically made of gold or aluminum with a diameter of about 25-μm and are quite fragile. Typically, bond wires have a large minimum radius of curvature at bends in the wire to avoid damage. Thus, the bond wires dictate the dimensions of the MLP, whereas the MLP may have a smaller profile without the bond wires. Further, care must be taken when over-molding the encapsulation layer as the wires may break under stress from the molding resin. The molding stress may also deform the bond wires, potentially causing short circuits.
One method for avoiding the issues with wire bonding is to affix stud bumps to the features on top of the semiconductor chip. The chip is then flipped over onto a leadframe, which includes conductors that connect the bumps with the leads. A drawback of such “flip chip” MLPs is that the leadframe must be specifically designed for the semiconductor chip applied to it. Particularly, the conductors and the leads must account for the number and the pattern of bumps on the chip. A change in the chip design, such as a higher density of features, may require a new leadframe design. Further, if different semiconductor chips are packaged on the same line, the specific leadframe for each chip must be carefully coordinated with the chips.
Therefore, what is needed is a method of manufacturing an MLP that is reliable and less expensive, while providing a leadframe that may be used for multiple semiconductor chip designs.